Served as technical management position in Silicon Image Inc. before founding UBEC in 2003.
Founded UBEC in 2003 and sold UBEC’s US subsidiary (Hyperband Communication Inc.) into MediaTek Inc. in 2005.
Vice President of MediatTek in USA for RF division and acted as technical consultant for MediaTek branch in Singapore and headquarters in Taiwan at the same period for 3G related cellular projects in 2005-2008.
（1）Vice President of RF, Analog and VLSI Department
Lead/Design Innovated Digital PLL (DPLL) project with smallest area at 0.1 mm^2 at TSMC 40 nm and 0.07 mm2 at TSMC 28 nm with RMS jitter around 2 ps. Two US patents are already issued for these designs 2013 Fellow of International Electrical Technology
Lead High Speed SerDes projects such as HDMI TX at 3.4 GHz, eDP (embeeded Display Portat 2.7 GHZ, MIPI DPHY TX/ CPHY RX at 1 GHz, and LVDS at 1 GHz. Patent single configurable multi-PHY chip for LVDS/eDP/MiPi.
Lead/Design 10/100 MHz Ethernet PHY at TSMC 40nm CMOS process
Design 100 MSPS 10 bits ADC at TSMC 40 nm CMOS process and TSMC 28 nm
process , SMIC 65 nm CMOS process
Design Low Noise Amplifier (LNA), Pre-PA (Driver for Power Amplifier), PA (Power Amplifier with output P1dB at 18 dBm) for 802. 11 N WLAN Transceiver at TSMC 40 nm CMOS process
（2）Vice Presidnt of RF and Analog Department at MediaTek (聯發科) USA
CEO of Hyperband Communication Inc. (HBC) from 2003 to 2005. Hyperband Ciommunication Inc. was merged into MediaTek Inc. at 2005.
managed team and led the development in wireless related projects, such as Bluetooth EDR 2.0 , WLAN, and WiMAX, for MediaTek Inc. He also acted as technical consultant for MediaTek branch in Singapore and headquarters in Taiwan at the same period for 3G related cellular projects
Manage MediaTek Inc. US RF/Analog division
Lead 802.11 N WLAN transceiver project at TSMC 0.13 um CMOS process
Lead Bluetooth 2.0 Transceiver project at TSMC 0.13 um CMOS process
Design WiMax receiver chain including LNA, Mixer, Trans-Impedance Amplifier, Filter and Programmable Gain Amplifier at TSMC 65 nm CMOS process
Help MediaTek Inc. do Technical Dual Diligence to invest or buy start-up companies
（3）Silicon Communication Lab (SCL) :Senior Manager, Senior Manager
V.P. of Silicon Communication Lab (SCL) from 1999 to 2000. Silicon Communication and handled R&D development for LCD front-end analog chip development in 1999
In 2000, the start-up company (SCL) was merged into Silicon Image Inc
He led the development for 160 MSPS 8 bits Nyquist Rate ADC and 1.6 GHz high-speed serial data transceiver for video related applications
Lead/Design SATA (Serial ATA) Standard 1.0/2.0 PHY portion of chip that running at 1.5GHz/3.0GHz
Design 160 MSPS 8 bits ADC using TSMC 0.35 um process for LCD Panel front end chips
Design Line Locked PLL for LCD Panel
He has published 5 technical papers and holds 24 US and Oversea
patents for the area of RF and Analog Integrated Circuits.